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Title:
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2002026093
Kind Code:
A
Abstract:

To perform highly accurate defect inspection while shortening the inspection time.

A patterned wafer where chips are formed in a pattern of integrated circuit including semiconductor elements is irradiated with an electron beam while scanning and secondary electrons emitted therefrom are detected in order to inspect the defect of the wafer using the electron beam image thereof. Such a method for inspecting the defect of a wafer comprises step K1 for acquiring an electron beam image by scanning the wafer while eliminating the number of scanning lines at a rate of 1/n, step K2 for extracting defect distribution of the wafer on an electron beam image thus obtained, step K3 for sampling a chip to be inspected based on the defect distribution, and step K4 for inspecting a sampled chip in detail. Since a defect distribution is determined from an electron beam image obtained by eliminating the number of scanning lines, a chip to be inspected is sampled based on the defect distribution, and then a sampled chip is inspected in detail, inspection accuracy can be enhanced while shortening the inspection time.


Inventors:
SAEKI KEIICHI
NOZOE MARI
WATANABE KENJI
HIJIKATA SHIGEAKI
INOUE JIRO
Application Number:
JP2000207821A
Publication Date:
January 25, 2002
Filing Date:
July 10, 2000
Export Citation:
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Assignee:
HITACHI LTD
HITACHI TOKYO ELECTRONICS
International Classes:
G01B21/30; G01N23/225; H01J37/147; H01L21/66; (IPC1-7): H01L21/66; G01B21/30; G01N23/225; H01J37/147
Attorney, Agent or Firm:
Kajiwara Tatsuya