PURPOSE: To reduce the capacity between source and drain regions and gate electrode in a silicon gate MOS transistor regardless of the depth of the source and drain regions by forming the gate electrode by two-layer polycrystalline silicon film when forming the transistor.

CONSTITUTION: A thick field SiO2 film 13 and a thin gate SiO2 film 14 surrounded by the film 13 are coated on a p-type silicon substrate 12, and a relatively thin polycrystalline silicon film 15 having n-type imourity and a relatively thick polycrystalline silicon film 16 having no impurity are laminated and grown on the entire surface thereof. Then, a pattern 17 of a resist film is formed on the film 16 at the center of the substrate 12, and with the pattern 17 as a mask the film 16 is etched to thereby retain only the gate electrode 19 made of the film 16. Then, with the electrode 19 as a mask it is etched to thereby form a pattern 18 formed by the film 15 under the electrode 19 and a pattern 20 formed by the film 14. With these patterns 18 and 20 as masks n-type source and drain regions 22 are diffused to be formed in the substrates 12 at both sides thereof.