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Title:
METHOD FOR FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2001250795
Kind Code:
A
Abstract:

To protect a gate oxide film against breakdown due to charge up damage by reducing inflow of plasma electrons, generated at the time of depositing a thin film by sputtering, to a semiconductor substrate.

In a process for making contact holes 23 in an insulation film 22 and depositing a barrier conductor film 24 on the surface of the insulation film 22 including the inside of the contact holes 23 by sputtering, means for reducing inflow of plasma electrons to a semiconductor substrate 1 is employed for depositing the barrier conductor film 24. As the means for reducing inflow of plasma electrons to the semiconductor substrate 1, a collimation sputtering system or a long throw sputtering system is employed.


Inventors:
FUKUDA NAOKI
ASHIHARA YOJI
Application Number:
JP2000058355A
Publication Date:
September 14, 2001
Filing Date:
March 03, 2000
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
C23C14/34; H01L21/203; H01L21/285; H01L21/8238; H01L27/092; H01L29/78; (IPC1-7): H01L21/285; C23C14/34; H01L21/203; H01L21/8238; H01L27/092; H01L29/78
Attorney, Agent or Firm:
Yamato Tsutsui