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Patent Searching and Data


Title:
METHOD OF FIXING ELECTRIC TERMINAL
Document Type and Number:
Japanese Patent JPS6041779
Kind Code:
A
Abstract:
A chip mounting device which is hereinafter also referred to as an "interconnection preform placement device", includes a retaining member having a predefined pattern of holes in which are positioned preforms of joint-forming material such as solder. Each preform is of a predefined configuration and has a height or length greater than is cross-sectional dimension. The preform retains its general configuration after the interconnection or soldering process to form a resilient joint which is more capable of withstanding stress, strain and fatigue. A method of forming resilient interconnections comprises placing the interconnection preform placement device between parallel patterns of electrically conductive elements, such as the conductive pads on an electronic component and a circuit board, and effecting the bonding of the conductive elements with the preforms.

Inventors:
WATANABE AKIRA
Application Number:
JP14983083A
Publication Date:
March 05, 1985
Filing Date:
August 17, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
B23K3/06; H01R9/16; B23K35/02; H05K3/32; H05K3/34; H05K13/04; H05K3/40; (IPC1-7): H01R9/16
Attorney, Agent or Firm:
Koshiro Matsuoka