Title:
MOSFET半導体装置の形成方法
Document Type and Number:
Japanese Patent JP4838976
Kind Code:
B2
Abstract:
A high power MOSFET semiconductor having a high breakdown voltage. The new power device concept that reaches an area of a lower specific on-resistance, higher breakdown voltage and reduced device silicon area. This device architecture is built on the concepts of charge compensation in the drift region of the device. Where, the doping of the vertical drift region is increased by one order of magnitude. To counterbalance the added charges, fine-structured wells of opposite doping type to the drift region are introduced as part of the device structure. The charge compensation wells do not contribute to the on-state current conduction, therefore, this novel new generation of high voltage device architecture breaks the limit line of silicon. This architecture may extend to higher material resistivity and larger geometry to increase the voltage to 1kv plus.
Inventors:
Abdul Em Erhatem
Application Number:
JP2003334487A
Publication Date:
December 14, 2011
Filing Date:
September 26, 2003
Export Citation:
Assignee:
XEROX CORPORATION
International Classes:
H01L29/78; H01L21/336; H01L29/06
Domestic Patent References:
| JP2001111041A | ||||
| JP2001119022A | ||||
| JP2000040822A |
Attorney, Agent or Firm:
Kenji Yoshida
Jun Ishida
Jun Ishida