Title:
METHOD FOR FORMING DIGITAL LOGICAL CIRCUIT
Document Type and Number:
Japanese Patent JPS61278972
Kind Code:
A
Abstract:
PURPOSE:To attain automatic assignment by refering a library in an intermediate circuit block group independent of a specific parts or device technology, and if there is no library coincident with the number of inputs of a macro circuit block, dividing the number of inputs and blocks. CONSTITUTION:When digital logical circuit information is inputted from an I/O device 1, an intermediate block retrieving means 41 selects a macro circuit block circuit A from a digital logical circuit at first, and then retrieves an intermediate circuit block library by using the function code and the number of inputs of the circuit A as keys. When coincident contents are detected, an intermediate circuit assigning means 43 assigns the coincident contents to corresponding parts. When the number of inputs in the macro circuit block is smaller than that of all the input circuit blocks, an intermediate block converting means 42 sets up a constant value in residual inputs. When the former is larger than the latter, the means 42 converts the intermediate circuit blocks existing in the library into L N-M decoders and a K-L decoder to form the circuit A.
Inventors:
MATSUMOTO IWASUKE
IWASE MASAKAZU
ISHIZAKI HISASHI
NIIMI FUMIHIKO
IWASE MASAKAZU
ISHIZAKI HISASHI
NIIMI FUMIHIKO
Application Number:
JP12102285A
Publication Date:
December 09, 1986
Filing Date:
June 04, 1985
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F17/50; (IPC1-7): G06F15/60
Attorney, Agent or Firm:
Shin Uchihara