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Title:
METHOD FOR FORMING ELEMENT SEPARATING SECTION AND MANUFACTURE OF SEMICONDUCTOR DEVICE USING THE METHOD
Document Type and Number:
Japanese Patent JPH02161766
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of masks required when a plurality of devices is formed on the same semiconductor substrate by forming a semiconductor layer of a conduction type opposite to that of the substrate of the same semiconductor as that forming an active area.

CONSTITUTION: N+ type buried layers 2 are selectively formed in the NPN transistor(Tr) area of a P type substrate 1 and an N type epitaxial layer 3 is formed on the substrate 1 and layers 2. P+ buried layers 4 and N type epitaxial layers 5 are piled up on element separating areas and NMOS Tr areas. Then an N and P diffused layers 6 and 7 are respectively formed in a PMOS and NMOS Tr areas. Thereafter, an SiO2 film 8 and Si3N4 film 9 are selectively formed and N+ diffused layers 10 are formed in field parts of the NPN Tr and PMOS Tr areas. In addition, P+ diffused layers 11 are formed in the NMOS TR and element separating areas. After forming the layers 11, field oxide films 12 are formed and the film 9 are removed. Thus the element separating areas are formed. Since the layers 7 are formed in the NMOS Tr and element separating areas in same process during the course the above-mentioned processes, the number of masks to be used for the processes can be reduced by one.


Inventors:
NEMOTO KIYOSHI
MIHARA TAKASHI
KANEKO SHINJI
NIWA TOSHIO
Application Number:
JP31487788A
Publication Date:
June 21, 1990
Filing Date:
December 15, 1988
Export Citation:
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Assignee:
OLYMPUS OPTICAL CO
International Classes:
H01L21/761; H01L21/76; H01L21/8249; H01L27/06; (IPC1-7): H01L21/76; H01L27/06
Attorney, Agent or Firm:
Kenji Mogami