Title:
半導体素子の金属配線層形成方法
Document Type and Number:
Japanese Patent JP4446726
Kind Code:
B2
Abstract:
The present invention is provided to form a metal line layer in a semiconductor device, wherein at least one conductive layer of a plurality of conductive layers is etched, a side wall oxide film is formed on side walls of some conductive layers of the etched conductive layers, and then the other conductive layers are etched. According to the present invention, since it is possible to prevent attacks against the side walls, which may occur due to sputtering and bending of plasma ions, it is possible to enhance yield and reliability of a semiconductor device.
Inventors:
Lee Shun
Application Number:
JP2003411499A
Publication Date:
April 07, 2010
Filing Date:
December 10, 2003
Export Citation:
Assignee:
MAGNACHIP SEMICONDUCTOR LTD
International Classes:
H01L21/28; H01L21/3213; H01L21/02; H01L21/3065; H01L21/3205; H01L21/44; H01L23/52
Domestic Patent References:
| JP7249611A | ||||
| JP11312681A | ||||
| JP2003133414A | ||||
| JP2000323483A | ||||
| JP2000353804A |
Attorney, Agent or Firm:
Hiroyuki Nakagawa
Sorimachi Yukiyoshi
Yuji Oishi
Kei Iwata
Hiroji Nakagawa
Sorimachi Yukiyoshi
Yuji Oishi
Kei Iwata
Hiroji Nakagawa