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Title:
METHOD FOR FORMING SIGNAL WIRING IN MULTILAYER INTERCONNECTION BOARD
Document Type and Number:
Japanese Patent JPH01107597
Kind Code:
A
Abstract:

PURPOSE: To prevent wire breakdown of a wiring pattern in a via hole, by depositing a thin film for plating electrodes, plating a thin conductor layer thereon, and thereafter patterning wirings by using light sensitive resist.

CONSTITUTION: A thin metal film 4 is formed on a lower signal wiring layer 1 and an organic insulating film 2 on a multilayer interconnection substrate 10 by a vacuum evaporating method or a sputtering method. Then a conductor metal layer 5 is formed by depositing a metal, e.g., gold or copper, which is used as wirings on the thin metal film 4 by electrolytic plating. Light sensitive resist 6 is applied on the conductor metal layer 5. Exposure is performed through a specified mask and development is performed. With the thin metal film 4 and the conductor metal layer 5 as plating electrodes, an upper signal wiring layer 8, whose metal is the same as the conductor metal layer 5, is formed by an electrolytic plating method. Then, the upper signal wiring layer 8 is used as etching resist, and conductor metal layer 5 and the thin metal film 4 are etched. Thus the wire breakdown in the wiring pattern in a via hole can be prevented.


Inventors:
OKADA YOSHITSUGU
Application Number:
JP26559487A
Publication Date:
April 25, 1989
Filing Date:
October 20, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
H05K3/46; (IPC1-7): H05K3/46
Attorney, Agent or Firm:
Uchihara Shin



 
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