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Title:
METHOD FOR FORMING SOLDER LAYER FOR DIE BONDING
Document Type and Number:
Japanese Patent JPH0272639
Kind Code:
A
Abstract:

PURPOSE: To shorten etching time by removing only the required regions of a thin contact metal layer which is formed on the rear surface of a semiconductor wafer beforehand by etching, thereafter attaching solder to the remaining regions of the contact metal layer corresponding to semiconductor element regions.

CONSTITUTION: Many semiconductor element regions 2 are formed in the surface of a semiconductor wafer 1. The semiconductor element regions 2 are divided with scribing lines 3 which are to become reference lines in dicing. A thin contact metal layer 4 is formed on the entire rear surface of the semiconductor wafer 1. Only the regions of the contact metal layer 4 corresponding to the scribing lines 3 are removed by etching. Thereafter, the rear surface side of the semiconductor wafer 1 is immersed into fused solder bath. Thus, the solder is attached to remaining regions 4b of the contact metal layer. In this way, the time required for the etching treatment can be shortened, and the dead loss of the solder can be reduced.


Inventors:
AKI YASUO
Application Number:
JP22394788A
Publication Date:
March 12, 1990
Filing Date:
September 07, 1988
Export Citation:
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Assignee:
ROHM CO LTD
International Classes:
H01L21/52; (IPC1-7): H01L21/52
Domestic Patent References:
JPS4940669A1974-04-16
JPS6248032A1987-03-02
JPS5864037A1983-04-16
Attorney, Agent or Firm:
Kazuhide Okada



 
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