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Patent Searching and Data


Title:
METHOD OF FORMING WIRING OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPH10125774
Kind Code:
A
Abstract:

To form a fine wiring at a high reliability by forming wiring grooves into a layer insulation film after planarizing, burying a wiring material for forming connection holes to a lower wiring or substrate, and forming a wiring to resolve the trouble of a resist entering holes.

On a substrate 30 a layer insulation film 44 is deposited and the surface is planarized. Wiring grooves are formed, a first wiring material 50 is deposited on the wiring grooves and insulation film 44 and patterned with a connection hole resist mask 52. Patterning of connection holes 56 to a lower wiring is made by a photo etching process which bores the first material 50 forming a wiring layer and insulation film 44 together. The insulation film 44 is etched to finish the connection holes 56. A conductive material is buried in the holes 56 and then a wiring 58 and connection plugs 60 are formed by a double machining process using a CMP apparatus.


Inventors:
SUZUKI YASUTSUGU
Application Number:
JP27318896A
Publication Date:
May 15, 1998
Filing Date:
October 16, 1996
Export Citation:
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Assignee:
KAWASAKI STEEL CO
International Classes:
H01L23/522; H01L21/768; (IPC1-7): H01L21/768
Attorney, Agent or Firm:
Satoshi Takaya (2 outside)