PURPOSE: To prevent a frequency-divided encoder pulse from being shifted from the original encoder pulse by providing a counter having the initial value N which is counted in synchronization with the leading and trailing edges of the encoder pulse.

CONSTITUTION: The encoder pulses (phase A) 1 and (phase B) 2 are inputted to a direction of revolution detection/phase A leading/trailing edge detection circuit 12 to generate a forward/reverse signal 4 and a phase A leading/trailing edge pulse. Then a U/D signal 15 is outputted from a count mode deciding circuit 14 to input a count-up pulse 17 and a count-down pulse 18 from a count pulse distributor 16 to a counter 19 having the initial value N. Moreover, the counter 19 and the count mode deciding circuit 14 are controlled by a signal from a preset pulse generating circuit 24 and a comparator 22 and a phase A frequency division pulse 27 is outputted from a 1/2 frequency divider circuit 26.