Title:
METHOD OF GENERATING TEST PLAN FOR ANALOG INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3672336
Kind Code:
B2
Abstract:
PURPOSE: To generate a test plan for each block of A/D or hybrid signal element or a circuit consisting of a combination of these elements by processing the blocks individually and performing the test and also trying a test method and a solution measure.
CONSTITUTION: For each block, a test plan generator 15 decides a circuit input value for generating the block input and also a circuit output value for the block output. That is, the circuit input generates values to be listed in a test model 13 in the block applicable. In this manner, the generator 15 generates a collection of circuit values with no contradiction to be applied and measured at the circuit level when the block is being tested. Calculation of the circuit values is made through circuit simulation using a matrix of a circuit equation. The result gives a test plan 16, where a known circuit input may be applied on an IC, and the output generated as a result therefrom can be compared with the expected result for the circuit.
Inventors:
Naiknaware Ravindranath
G-Nandakumar
Srinivasa Earl Casa
G-Nandakumar
Srinivasa Earl Casa
Application Number:
JP1286894A
Publication Date:
July 20, 2005
Filing Date:
February 04, 1994
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
G01R31/28; G01R31/316; G01R31/3167; G01R31/317; G01R31/3183; G01R31/26; H01L21/66; (IPC1-7): G01R31/316; G01R31/26; G01R31/3183; H01L21/66
Domestic Patent References:
JP5006404A | ||||
JP4074272A |
Attorney, Agent or Firm:
Minoru Nakamura
Fumiaki Otsuka
Shishido Kaichi
Hideto Takeuchi
Toshio Imajo
Nobuo Ogawa
Village shrine Atsuo
Fumiaki Otsuka
Shishido Kaichi
Hideto Takeuchi
Toshio Imajo
Nobuo Ogawa
Village shrine Atsuo
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