Title:
METHOD FOR IMPROVING PARALLELISM OF INSTRUCTION EXECUTION AND DEVICE THEREFOR
Document Type and Number:
Japanese Patent JP3160259
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve parallelism execution of an instruction by permitting the execution of each instruction updating and using an integral exceptional register(XER) in out-of-order.
SOLUTION: In a central processing unit having a pipeline architecture, an integral instruction using and updating an XER can be executed in out-of- order by using an XER rename mechanism. An instruction updating the XER is provided with a corresponding instruction identifier(IID) stored in a register. The following instruction using the data in the XER decides the point of time of the update of the XER data by an instruction corresponding to the IID. When each instruction updating the XER data is executed, the data are stored in an XER rename buffer, and an instruction using the XER data afterwards obtains the updated valid XER data from the rename buffer.
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Inventors:
Richard Edmond Fry
Doug Quoc Guen
Albert Thomas Williams
Doug Quoc Guen
Albert Thomas Williams
Application Number:
JP2620299A
Publication Date:
April 25, 2001
Filing Date:
February 03, 1999
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
G06F9/38; (IPC1-7): G06F9/38
Domestic Patent References:
| JP8123685A | ||||
| JP7334362A | ||||
| JP1142831A | ||||
| JP5282254A |
Other References:
【文献】米国特許5751985(US,A)
Attorney, Agent or Firm:
Jiro Yamamoto (2 outside)