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Patent Searching and Data


Title:
METHOD FOR INSPECTING POLYCRYSTALLINE SILICON MEMBRANE TRANSISTOR
Document Type and Number:
Japanese Patent JP2000097987
Kind Code:
A
Abstract:

To realize an inspecting method capable of accurately inspecting the reliability of a polycrystalline silicon membrane transistor.

The source and drain of a polycrystalline silicon membrane transistor 10b provided in a liquid crystal display are grounded, and a positive voltage of 10 V or higher is impressed to the gate. The polycrystalline silicon membrane transistor 10b is simultaneously maintained at temperatures equal to room temperature or higher for a predetermined time to impress stress. The amount of fluctuation in the threshold values of the polycrystalline silicon membrane transistor 10b prior to and after the impression of such voltage and temperature stress is measured, and its reliability is determined according to the amount of fluctuation in the measured threshold values.


Inventors:
SUZUKI MITSUAKI
Application Number:
JP27201898A
Publication Date:
April 07, 2000
Filing Date:
September 25, 1998
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L29/786; G01R31/26; G02F1/13; G02F1/136; G02F1/1368; H01L21/66; (IPC1-7): G01R31/26; G02F1/13; G02F1/136; H01L21/66; H01L29/786
Attorney, Agent or Firm:
Takehiko Suzue (6 outside)