Title:
METHOD FOR MANUFACTURE OF N-CHANNEL CLAMP FOR ESD PROTECTION USE DURING SELF-ALIGNED SILICIDE CMOS PROCESS INTEGRATED CIRCUIT DEVICE PROVIDED WITH SAID CLAMP
Document Type and Number:
Japanese Patent JPH04229649
Kind Code:
A
Abstract:
PURPOSE: To reduce damages to a CMOS integrated circuit which has self- matching silicified source and drain regions by stopping silicification near the gate of a transistor for electrostatic discharge protection by using a deposited oxide layer as a mask. CONSTITUTION: At the same time as with sidewall spacers 24 and 25, an oxide layer 30 is formed on a gate 20 of a transistor 11 for electrostatic discharge protection and the top part of its drain region 19. This layer 30 stops a self- matching silicified region from being formed in contact with the gate. The entire surface of a wafer after the silicified area has been formed is covered with an oxide layer 33 which is deposited at low temperature, and photoresist masking and etching are carried out to open a bias for contact with the silicified area in contact regions 38 and 39. Then metallized layers 34, 35, 36, and 38 for interconnecting are formed of such metal as aluminum.
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Inventors:
KAIZAADO RAMII MISUTORII
Application Number:
JP8814491A
Publication Date:
August 19, 1992
Filing Date:
April 19, 1991
Export Citation:
Assignee:
DIGITAL EQUIPMENT CORP
International Classes:
H01L21/822; H01L21/8238; H01L27/04; H01L27/02; H01L27/092; H01L29/45; (IPC1-7): H01L27/04; H01L27/092
Domestic Patent References:
| JPH01259560A | 1989-10-17 | |||
| JPS62213277A | 1987-09-19 |
Attorney, Agent or Firm:
Minoru Nakamura (7 outside)