METHOD OF MANUFACTURING CMOS DEVICE HAVING TWO WORK FUNCTIONS

Title:

METHOD OF MANUFACTURING CMOS DEVICE HAVING TWO WORK FUNCTIONS

Document Type and Number:

Japanese Patent JP2008211182

Kind Code:

A

Abstract:

To provide a method of manufacturing a semiconductor device with two work functions.

A manufacturing method includes a step of providing a device on a first region and a second region of a substrate. The step includes providing a dielectric layer on the first region and the second region of the substrate, and providing a gate electrode above the dielectric layer of both the first and second regions. Both the gate electrodes on the first and second regions respectively have a work function. The method further includes providing a capping layer on the first region between the dielectric layer and the gate electrode to change the work function of the gate electrode on the first region, and embedding species so as to introduce the species at an interface between the dielectric layer and the gate electrode in the second region to change the work function of the gate electrode on the second region.

Inventors:

CHANG SHOU-ZEN
YU HONG YU
VELOSO ANABELA
VOS RITA
KUBICEK STEFAN
BIESEMANS SERGE
SINGANAMALLA RAGHUNATH
LAUWERS ANNE
ONSIA BART

Application Number:

JP2008002367A

Publication Date:

September 11, 2008

Filing Date:

January 09, 2008

Export Citation:

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Assignee:

IMEC INTER UNI MICRO ELECTR
TAIWAN SEMICONDUCTOR MFG

International Classes:

H01L21/8238; H01L21/283; H01L21/306; H01L21/314; H01L27/092; H01L29/423; H01L29/49; H01L29/78

Domestic Patent References:

JP2006222385A	2006-08-24
JP2006344713A	2006-12-21
JP2006108439A	2006-04-20
JP2003309188A	2003-10-31
JP2005093815A	2005-04-07
JP2004228180A	2004-08-12
JP2003282875A	2003-10-03
JP2005252192A	2005-09-15

Foreign References:

WO2005122286A2

2005-12-22

Attorney, Agent or Firm:

Takuji Yamada
Mitsuo Tanaka
Haruo Nakano

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