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Title:
METHOD FOR MANUFACTURING DMOS-TYPE TRANSISTOR
Document Type and Number:
Japanese Patent JP2002217412
Kind Code:
A
Abstract:

To provide a method for manufacturing a DMOS type transistor which can shorten the time of diffusion required for forming a body diffused layer and reduce the influence on the concentration profile of a channel stopper.

An N- type area 121 as a drift area of a DMOS transistor and an N- type 122 as the other element area thereof are formed in a silicon substrate 11. A P+ area 13 beneath an element isolation insulating film 14 is a channel stopper. The DMOS transistor is processed by a gate oxidizing step (for a gate oxide film 15) and a gate electrode 16 is patterned. Next, a resist 18 is formed and P+ type body diffused layer 17 is formed. In this case, a source region is formed by a mask including a gate electrode that is formed later adjacent to the gate electrode 16 and an offset distance can be obtained, so that a time of diffusion required for forming the P+ type body diffused layer 17 may be about the duration of extending it adjacent to the end part of the gate electrode 16.


Inventors:
SATO AKIRA
Application Number:
JP2001008710A
Publication Date:
August 02, 2002
Filing Date:
January 17, 2001
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H01L29/78; H01L21/336; H01L21/8234; H01L27/08; H01L27/088; (IPC1-7): H01L29/78; H01L21/8234; H01L27/08; H01L27/088
Attorney, Agent or Firm:
Masanori Ueyanagi (1 outside)