Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
METHOD FOR MANUFACTURING FLASH MEMORY ELEMENT
Document Type and Number:
Japanese Patent JP2007318073
Kind Code:
A
Abstract:

To provide a method for manufacturing a flash memory with a short gate length for preventing punch-through leakage currents generated between cell joints.

This method for manufacturing a flash memory element includes a step for forming a gate 112 at the upper part of a semiconductor substrate 100 whose cell region, low voltage region, and high voltage region are defined, for carrying out an ion implantation process by opening only the cell region, and for forming cell junction in the semiconductor substrate; a step for carrying out a first heat treatment process, and for carrying out low density ion implantation process by opening only the low voltage region; a step for carrying out the ion implantation process by opening the high voltage region, and for forming a spacer 120 on the side face of the gate; and a step for carrying out a high density ion implantation process by opening only the low voltage region, and for carrying out a second heat treatment process.

COPYRIGHT: (C)2008,JPO&INPIT


Inventors:
BOKU HEISHU
Application Number:
JP2007005305A
Publication Date:
December 06, 2007
Filing Date:
January 15, 2007
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
HYNIX SEMICONDUCTOR INC
International Classes:
H01L21/8247; H01L21/8234; H01L27/088; H01L27/10; H01L27/115; H01L29/78; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Hiroyuki Nakagawa