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Title:
METHOD FOR MANUFACTURING HETERO-JUNCTION FIELD EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JP2004281720
Kind Code:
A
Abstract:

To provide a hetero-junction field effect transistor by which plasma damage of a reactive ion or the like entering a crystal due to dry etching for selective removal of an insulation layer or a semiconductor layer above a barrier layer is suppressed in a crystal structure, where the barrier layer with a larger atomic weight than an electron supply layer is formed on the electron supply layer of the hetero-junction field effect transistor.

This method is used to prevent degrading of device electric characteristic in such a material where the atomic weight of a barrier layer is at least larger than that of an electron supply layer in a crystal structure of the hetero-junction field effect transistor, and to suppress electron mobility and carrier concentration lowering rate at 90% or more by entering the barrier layer with an atomic weight 1.5 times or more that of the electron supply layer so that reactive ions such as F, S, Cl, etc. resulting from an etching gas entering the crystal due to dry etching may be suppressed.


Inventors:
TANIGUCHI TAKAFUMI
UCHIYAMA HIROYUKI
Application Number:
JP2003071193A
Publication Date:
October 07, 2004
Filing Date:
March 17, 2003
Export Citation:
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Assignee:
RENESAS TECH CORP
International Classes:
H01L29/812; H01L21/338; H01L29/778; (IPC1-7): H01L21/338; H01L29/778; H01L29/812
Attorney, Agent or Firm:
Yasuo Sakuta