Title:
集積回路装置の製造方法及び酸化バナジウム膜の形成方法
Document Type and Number:
Japanese Patent JP4620962
Kind Code:
B2
Abstract:
A vanadium oxide film is formed on an interlayer insulating layer, and a silicon oxide film and a silicon nitride film are formed on the vanadium oxide film in this order. With a resist pattern used as a mask, the silicon nitride film is patterned. Then, the resist pattern is removed using a stripping solution or oxygen plasma ashing. Next, with the patterned silicon nitride film used as a mask, the silicon oxide film and the vanadium oxide film are etched to form a resistor film of vanadium oxide.
Inventors:
Naokawa Kawahara
Hirose Murase
Hiroaki Okubo
Yasutaka Nakashiba
Naoki Oda
Tokuto Sasaki
Nobukazu Ito
Hirose Murase
Hiroaki Okubo
Yasutaka Nakashiba
Naoki Oda
Tokuto Sasaki
Nobukazu Ito
Application Number:
JP2004101108A
Publication Date:
January 26, 2011
Filing Date:
March 30, 2004
Export Citation:
Assignee:
Renesas Electronics Corporation
NEC
NEC
International Classes:
H01L21/3065; H01L21/822; H01L21/02; H01L21/316; H01L21/3213; H01L21/8234; H01L27/04; H01L37/00; H01L47/00; H01L23/522
Domestic Patent References:
| JP11074545A | ||||
| JP2002048636A |
Attorney, Agent or Firm:
Kimura Mitsuru