METHOD OF MANUFACTURING MULTILAYER WIRING BOARD

Japanese Patent JP3817463

B2

PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer wiring board which is capable of concurrently forming a plurality of thin film capacitors by selectively anodizing the limited area of a conductor pattern and making products decrease in fraction defective. SOLUTION: The surface of a conductor pattern 3 except the lower electrode forming region 17 of a thin film capacitor element 12 is covered with a first resist film 13, and a metal film layer 5 is formed on all the surface of the conductor pattern 3. Then, the first resist film 13 is separated, the metal film layer 5 is removed from the surface of the conductor pattern 3 except the lower electrode forming region 17, the surface of the conductor pattern 3 except the metal film layer 5 deposited on a part which is to serve as a lower electrode 4 is covered with a second resist film 14, and an anodized film 6 is formed on the metal film layer 5 exposed from the second resist film 14. Then, the second resist film 14 is separated, a contact/seed layer 15 is deposited on surfaces of the anodized film 6 and the metal film 5, and a conductor pattern 8 is formed on the anodized film 6 to serve as an upper electrode.