METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - SEMICONDUCTOR LEADING EDGE TEC

Title:

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Document Type and Number:

Japanese Patent JP2005203429

Kind Code:

A

Abstract:

To provide a method of manufacturing a semiconductor device which avoids the formation of a damaged layer on the side wall of a wiring trench and also increasing a damaged layer formed on the interface in a dry etching process and an ashing process.

The method comprises steps for forming first, second and third insulation films 2, 3 and 4, an antireflection film 5 and a resist film 6 one above another on lower layer wiring 1, dry-etching the third and second insulation films 4, 3 with the resist film 6 used as a mask, then ashing the resist film 6 and the antireflection film 5 to be removed, and dry-etching the first insulation film 2 with the third insulation film 4 used as a mask to form a wiring trench extending to the lower wiring 1. The dry etching is done with at least either hydrogen gas or inert gas added to a fluorocarbonic gas. The ashing uses at least either hydrogen gas or inert gas.

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Inventors:

SODA EIICHI

Application Number:

JP2004005581A

Publication Date:

July 28, 2005

Filing Date:

January 13, 2004

Export Citation:

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Assignee:

SEMICONDUCTOR LEADING EDGE TEC

International Classes:

H01L21/28; H01L21/3065; H01L21/311; H01L21/3205; H01L21/44; H01L21/4763; H01L21/768; H01L23/52; H01L23/522; (IPC1-7): H01L21/768; H01L21/28; H01L21/3065; H01L21/3205

Attorney, Agent or Firm:

Mamoru Takada
Hideki Takahashi
Atsuko Oaku

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