To reduce processing step number for forming upper-layer rewiring of a semiconductor device by forming the upper-layer rewiring with a method other than electroplating.
A semiconductor construction body 2 which is called a CSP is bonded on the upper surface center of a base plate 1 via an adhesive layer 3. A rectangular frame-shaped insulating layer 14 composed of a resin is formed on the upper surface of the base plate 1 in such a way that the upper surface of the insulating layer forms almost the same plane as the upper surface of the semiconductor construction body 2. On the upper surface of the semiconductor construction body 2 and of the insulating layer 14, an insulating film 15 composed of a prepreg material is formed with its upper surface flat. The upper-layer rewiring 16 formed by patterning a metal plate is formed on predetermined places of the upper surface of the insulating film 15. In this case, frustum-shaped protruding electrodes 17 formed integrally on the lower surface of the upper-layer rewiring 16 encroach on the insulating film 15 to make them contact respectively to the upper surface centers of pillar-shaped electrodes 12.
WAKIZAKA SHINJI
JPH1032224A | 1998-02-03 | |||
JP2002176235A | 2002-06-21 |