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Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2007123941
Kind Code:
A
Abstract:

To reduce processing step number for forming upper-layer rewiring of a semiconductor device by forming the upper-layer rewiring with a method other than electroplating.

A semiconductor construction body 2 which is called a CSP is bonded on the upper surface center of a base plate 1 via an adhesive layer 3. A rectangular frame-shaped insulating layer 14 composed of a resin is formed on the upper surface of the base plate 1 in such a way that the upper surface of the insulating layer forms almost the same plane as the upper surface of the semiconductor construction body 2. On the upper surface of the semiconductor construction body 2 and of the insulating layer 14, an insulating film 15 composed of a prepreg material is formed with its upper surface flat. The upper-layer rewiring 16 formed by patterning a metal plate is formed on predetermined places of the upper surface of the insulating film 15. In this case, frustum-shaped protruding electrodes 17 formed integrally on the lower surface of the upper-layer rewiring 16 encroach on the insulating film 15 to make them contact respectively to the upper surface centers of pillar-shaped electrodes 12.


Inventors:
WAKABAYASHI TAKESHI
WAKIZAKA SHINJI
Application Number:
JP2007029902A
Publication Date:
May 17, 2007
Filing Date:
February 09, 2007
Export Citation:
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Assignee:
CASIO COMPUTER CO LTD
International Classes:
H01L23/12; H01L21/60
Domestic Patent References:
JPH1032224A1998-02-03
JP2002176235A2002-06-21