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Patent Searching and Data


Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2011210905
Kind Code:
A
Abstract:

To provide a semiconductor device of a MOS transistor having a trench structure facilitating an appropriate adjustment of a thereshold value of a channel region.

In a MOS transistor having a trench structure in which a concave region with its depth varied in a gate width direction and the concave region of a convex region are formed in the trench structure on a first conductive type semiconductor substrate, and a first conductive doped polysilicon film formed through a sacrifice oxide film formed along the surface of the first conductive type semiconductor substrate is embedded in the trench structure of the concave region and heat treated, diffusing impurities on an upper face of the convex region between the trench structures and on the side face and the bottom face of the concave part region of the trench structure. This facilitates a uniform impurity doping to a channel even for reduced trench pitches.


Inventors:
HASHITANI MASAYUKI
Application Number:
JP2010076376A
Publication Date:
October 20, 2011
Filing Date:
March 29, 2010
Export Citation:
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Assignee:
SEIKO INSTR INC
International Classes:
H01L29/78
Attorney, Agent or Firm:
Kentaro Kuhara
Noriaki Uchino
Nobuyuki Kimura