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Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2012146892
Kind Code:
A
Abstract:

To suppress the lowering of the strength of a semiconductor device.

The method comprises: a step (a) in which a surface 3a, a plurality of chip regions 10c formed on the surface 3a, dicing regions formed between chip regions 10c, and a surface 3a of a wafer ( semiconductor wafer ) 10 having a rear surface opposite to the surface 3a are fixed to a supporting member 15; a step (b) in which the rear surface of the wafer 10 is ground and the rear surface 3b is exposed in the state that the wafer 10 is fixed to the supporting member 15; a step (c) in which the wafer 10 is divided for each chip region 10c in the state that the wafer 10 is fixed to the supporting member 15; a step (d) in which a side surface 3c of the chip region 10c is etched, a crushed layer formed on the side surface 3c by the step (c) is removed, and a plurality of semiconductor chips are formed; and a step (e) in which, after the step (d), a plurality of divided chip regions 10c are removed from the supporting member 15 to obtain a plurality of semiconductor chips.


Inventors:
ABE YOSHIYUKI
MIYAZAKI CHUICHI
UEMATSU SHUNEI
SHIMAMOTO HARUO
Application Number:
JP2011005546A
Publication Date:
August 02, 2012
Filing Date:
January 14, 2011
Export Citation:
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Assignee:
RENESAS ELECTRONICS CORP
International Classes:
H01L21/301; H01L21/304; H01L21/3205; H01L21/768; H01L23/522; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
JP2004207607A2004-07-22
JP2004140179A2004-05-13
JP2008130705A2008-06-05
JP2005332982A2005-12-02
Attorney, Agent or Firm:
Yamato Tsutsui
Atsushi Sugada
Akiko Tsutsui
Toru Nakahara
Tetsuya Sakaji