Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3855793
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device which can restrain proximity effect and loading effect in forming a gate electrode and reduce parasitic capacitance.
SOLUTION: After a trench type element isolation region 2 surrounding an active region is formed in a semiconductor substrate 1, a gate insulating film 3 and a polycrystalline silicon film 4 are formed sequentially on the substrate 1. Resist 5 composed of resist 5a for forming a gate electrode and resist 5b for forming a dummy pattern is formed on the polycrystalline silicon film 4. The resist 5 is used as a mask and the silicon film 4 is etched, thereby forming a gate electrode 4a and a dummy pattern 4b. After the resist 5 is eliminated, the dummy pattern 4b is exposed by using a photolithography method, and resist 6 covering the gate electrode 4a is formed. After that, the resist 6 is used as a mask, and the dummy pattern 4b is etched and eliminated.
Inventors:
Junji Hirase
Application Number:
JP2002039513A
Publication Date:
December 13, 2006
Filing Date:
February 18, 2002
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G03F7/20; H01L29/78; H01L21/027; H01L21/28; H01L21/8234; H01L27/088; H01L29/417; (IPC1-7): H01L29/78; G03F7/20; H01L21/027; H01L21/28; H01L21/8234; H01L27/088; H01L29/417
Domestic Patent References:
| JP10200109A | ||||
| JP4127538A |
Attorney, Agent or Firm:
Fumio Iwahashi
Hiroki Naito
Daisuke Nagano
Hiroki Naito
Daisuke Nagano