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Patent Searching and Data


Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP2003077868
Kind Code:
A
Abstract:

To prevent the generation of splits and cracks in a wafer or a chip component, in a method for manufacturing a semiconductor integrated circuit using a wafer whose thickness is not more than 100 μm.

An extensible sheet 3 on which UV curing resin 2 is spread and a dicing sheet 5 where thermosetting resin 4 is spread on the surface are stuck on a back and a surface of the wafer 1 whose thickness is not more than 100 μm, and pressing is performed uniformly. The chip component 1a is isolated by using a dicing blade 6, and adhesive property of the UV curing resin 2 is reduced through irradiation of UV rays. The chip component 1a is exfoliated from the extensible sheet 3 by a pushing-up means 7, sucked by a suction means 8, pressed for a definite time against the surface of a dice pad 11 of a lead frame mounted on a heating means 7 via adhesive agent 9, and subjected to die bonding. The dicing sheet 5 is exfoliated from the surface of the chip component 1a by reducing the adhesive properties of the thermosetting resin 4.


Inventors:
FUJIMOTO HITOSHI
Application Number:
JP2001269677A
Publication Date:
March 14, 2003
Filing Date:
September 06, 2001
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/67; H01L21/301; H01L21/68; H01L21/683; (IPC1-7): H01L21/301; H01L21/68
Attorney, Agent or Firm:
Toshihide Kodama (3 others)