Title:
METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP2010073773
Kind Code:
A
Abstract:
To provide a technology of further uniformly embedding an adjacent trench arrangement part by solving problems wherein, whereas a silicon oxide-based embedding insulation film is flattened generally by simultaneously progressing film formation and sputter etching by HDP-CVD in a trench embedding process by a silicon oxide member in STI, it becomes increasingly difficult to uniformly embed adjacent trenches in a minute product of a 65 nm process node or the like.
When embedding an adjacent trench arrangement part with a silicon oxide-based embedding insulation film by HDP-CVD, a flat embedding performance is obtained by alternately repeating a film formation step and etching in a gaseous atmosphere including an etching gas.
Inventors:
HOTTA KATSUHIKO
NAKAMURA TAKAHIRO
OBA NAOYA
IWASAKI MASANOBU
NAKAMURA TAKAHIRO
OBA NAOYA
IWASAKI MASANOBU
Application Number:
JP2008237544A
Publication Date:
April 02, 2010
Filing Date:
September 17, 2008
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
H01L21/76; C23C16/42; C23C16/50; H01L21/31; H01L21/316; H01L27/08
Domestic Patent References:
| JP2007305981A | 2007-11-22 | |||
| JP2006190784A | 2006-07-20 | |||
| JP2007214278A | 2007-08-23 | |||
| JP2008547224A | 2008-12-25 | |||
| JP2005302848A | 2005-10-27 |
Foreign References:
| WO2007001878A2 | 2007-01-04 |
Attorney, Agent or Firm:
Shizuyo Tamamura