Title:
METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED- CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3913108
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To shorten a manufacturing TAT when memory data of a mask ROM loaded on a semiconductor integrated-circuit device of a multi-layer wiring structure is changed, and to improve a manufacturing yield.
SOLUTION: The manufacturing of a semiconductor integrated-circuit device having, for example, five layers for wiring layers is conducted as follows. In a sample production phase in which the data written into the mask ROM are often changed, the top layer of the fifth metal wiring layer is used for a bit line, and an interlayer insulating layer immediately thereunder is used for a forming layer of a via hole for writing data to shorten the manufacturing TAT. In a mass production phase in which the ROM data have been determined, the lowest layer of the first metal wiring layer M1 is formed for the bit line, and the interlayer insulating layer Z1 immediately thereunder is used for a forming layer of a via hole V1 for writing data to reduce the number of the layers constituting a memory cell. The manufacturing yield is improved by reducing the number of manufacturing steps of the memory cell.
Inventors:
Mitsuaki Hayashi
Shuji Nakaya
Shuji Nakaya
Application Number:
JP2002147878A
Publication Date:
May 09, 2007
Filing Date:
May 22, 2002
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L27/10; H01L21/8246; H01L27/112; (IPC1-7): H01L21/8246; H01L27/112
Domestic Patent References:
| JP58027359A | ||||
| JP2024563U | ||||
| JP2000299394A |
Attorney, Agent or Firm:
Akio Miyai
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