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Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE
Document Type and Number:
Japanese Patent JP2004071836
Kind Code:
A
Abstract:

To provide a method for manufacturing a semiconductor substrate by which the occurrence of a defective product due to particles and flaws resulted from a substrate holding jig can be reduced.

The semiconductor substrate is held by a susceptor and it is heated by a heat treatment device. At this point, particles on the supporting surface of the susceptor for the substrate are displaced to the backside of the substrate, and they are baked onto the surface thereof by heat while the substrate is heated. In addition, flaws are caused in the outer periphery of the rear side of the substrate, and particles generating accompanied with the flaws are baked. Then, the backside of the heated semiconductor substrate is removed by only a small quantity. In this case, the particles and flaws baked onto the backside of the substrate are removed. As a result, the occurrence of defective semiconductor substrates and defective devices due to the particles or flaws can be reduced.


Inventors:
ADACHI HISASHI
Application Number:
JP2002229192A
Publication Date:
March 04, 2004
Filing Date:
August 06, 2002
Export Citation:
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Assignee:
SUMITOMO MITSUBISHI SILICON
International Classes:
H01L21/762; H01L21/02; H01L21/324; H01L27/12; (IPC1-7): H01L21/324; H01L21/02; H01L21/762; H01L27/12
Domestic Patent References:
JPH09181026A1997-07-11
JP2002134521A2002-05-10
JPH08264626A1996-10-11
JPH11204493A1999-07-30
JPH08330398A1996-12-13
Attorney, Agent or Firm:
Ichiro Abe