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Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JP2001338899
Kind Code:
A
Abstract:

To provide a semiconductor wafer having a very small region of a peripheral sag or not having the peripheral sag at all.

A method for manufacturing the semiconductor wafer comprises the steps of slicing a semiconductor ingot to wafers, at least chamfering the wafer, flattening the wafer, primarily polishing the wafer and finish polishing the wafer in such a manner that a diameter of the wafer before the primary polishing is larger than that of a product wafer. The method further comprises the steps of radially contracting and chamfering the wafer by removing a peripheral part of the wafer up to the diameter of the product before the finish polishing. The ingot is preferred to have a diameter larger by 2 mm than that of the product. In the method, the ingot having a diameter larger by 2 mm than that of the product is sliced, a diameter of the wafer before the primary polishing is larger by 1 mm or more than that of the product, and a surface of the wafer before the radially contracting and the chamfering of the wafer is coated with a protective film.


Inventors:
Kitagawa, Koji
Application Number:
JP2000000157072
Publication Date:
December 07, 2001
Filing Date:
May 26, 2000
Export Citation:
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Assignee:
SHIN ETSU HANDOTAI CO LTD
International Classes:
B24B9/00; H01L21/304; (IPC1-7): H01L21/304; B24B9/00