Title:
METHOD FOR MANUFACTURING SILICON WAFER, SILICON WAFER AND SOI WAFER
Document Type and Number:
Japanese Patent JP2003229392
Kind Code:
A
Abstract:
To provide a method for manufacturing a silicon wafer in which the surface roughness and the overall flatness of a wafer can be prevented from deteriorating, and a silicon wafer manufactured by that method.
The method for manufacturing a silicon wafer comprises a process for lapping with a loose abrasive, and a process for etching with alkaline etching liquid wherein a loose abrasive having a maximum grain size of 21 μm or less and a mean grain size of 8.5 μm or less is employed in the lapping process and an alkaline aqueous solution having the concentration of an alkaline component not lower than 50 wt.% is employed as the alkaline etching liquid in the etching process. A silicon wafer manufactured by that method is also included.
Inventors:
IIZUKA NAOTO
NIHONMATSU TAKASHI
YOSHIDA MASAHIKO
MIYAZAKI SEIICHI
NIHONMATSU TAKASHI
YOSHIDA MASAHIKO
MIYAZAKI SEIICHI
Application Number:
JP2002306689A
Publication Date:
August 15, 2003
Filing Date:
October 22, 2002
Export Citation:
Assignee:
SHINETSU HANDOTAI KK
NAGANO ELECTRONICS IND
NAGANO ELECTRONICS IND
International Classes:
B24B37/00; B24B37/04; C09K13/02; C09K13/08; H01L21/02; H01L21/762; H01L21/302; H01L21/304; H01L21/306; H01L21/308; H01L27/12; (IPC1-7): H01L21/304; H01L21/02; H01L21/308; H01L21/762; H01L27/12
Attorney, Agent or Firm:
Mikio Yoshimiya