Title:
METHOD FOR MANUFACTURING SYSTEM ON CHIP AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2002043435
Kind Code:
A
Abstract:
To realize a high reliability of a thick film gate insulator in a peripheral circuit in a semiconductor device such as a system on chip that comprises the peripheral circuit where a MOS having the thick film gate insulator of a laminating body consisting of a first silicon oxide (a first gate insulator) 106 and a second silicon oxide (a second gate insulator) 110 is arranged and an internal circuit where a MOS having a thin film gate insulator consisting of the second silicon oxide 110 is arranged.
A silicon substrate is cleaned in the condition that the etching quantity of the first silicon oxide 106 in a region 102 where the peripheral circuit is formed is made 0.01 to 0.2 nm in film thickness.
Inventors:
SUZUKI TATSUYA
Application Number:
JP2000227065A
Publication Date:
February 08, 2002
Filing Date:
July 27, 2000
Export Citation:
Assignee:
NEC CORP
International Classes:
H01L21/336; H01L21/304; H01L21/306; H01L21/311; H01L21/316; H01L21/8234; H01L27/088; (IPC1-7): H01L21/8234; H01L21/304; H01L21/306; H01L21/316; H01L27/088
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)