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Title:
METHOD FOR MANUFACTURING THIN FILM TRANSISTOR
Document Type and Number:
Japanese Patent JP2005072292
Kind Code:
A
Abstract:

To improve transistor characteristics of the polysilicon thin film transistor of an LDD structure.

A method for manufacturing a thin film transistor implants phosphorus ions on a polysilicon thin film at high concentration when manufacturing the NMOS polysilicon thin film transistor, next, activates them by furnace annealing treatment, then, implants the phosphorus ions on the polysilicon thin film at low concentration, and then obtains an inventive product having Vg-Id characteristics shown in a full line by activating them by heat treatment in a high pressure water vapor atmosphere. For comparison, the phosphorus ions are implanted on the polysilicon thin film at the high concentration, next, they are implanted on the polysilicon thin film at the low concentration, and then the inventive product having Vg-Id characteristics shown in a dotted line can be obtained by activating them by furnace annealing treatment. In the case, it is possible to obtain one-place improvement in on-state current.


Inventors:
TOYAMA TADAHISA
Application Number:
JP2003300699A
Publication Date:
March 17, 2005
Filing Date:
August 26, 2003
Export Citation:
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Assignee:
CASIO COMPUTER CO LTD
International Classes:
G02F1/1368; H01L21/265; H01L21/336; H01L29/786; (IPC1-7): H01L21/336; G02F1/1368; H01L21/265; H01L29/786
Attorney, Agent or Firm:
Hanawa Yoshio