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Title:
METHOD FOR MANUFACTURING ULTRA THIN BODY FIELD EFFECT TRANSISTOR (FET) AND ULTRA-THIN BODY FET DEVICE (ULTRA-THIN BODY SUPER-STEEP RETROGRADE WELL (SSRW) FET DEVICE) MANUFACTURED BY THE SAME
Document Type and Number:
Japanese Patent JP2006049897
Kind Code:
A
Abstract:

To provide a method for manufacturing a super-steep retrograde well field effect transistor device, and to provide an ultra-thin body FET device manufactured by the same.

The method for manufacturing a super-steep retrograde well field effect transistor device starts with an SOI layer formed on a substrate, for example, an embedded oxide layer. The SOI layer is thinned so as to form an ultra-thin SOI layer. A separation trench is formed for dividing the SOI layer into an N ground layer region and a P ground layer region. The N and P ground layer regions formed in the SOI layer are doped with N-type and P-type dopants to a high concentration level. A semiconductor channel region is formed on the N and P ground layer regions. The source region and the drain region of the FET and the gate electrode stack on the channel region are formed. As desired, a diffusion retarding layer is formed between the SOI ground layer regions and the channel regions.


Inventors:
DAINE C BOYD
HOLT JUDSON R
LEONG MEIKEI
MO RENEE T
REN ZHIBIN
SHAHIDI GHAVAM G
Application Number:
JP2005219835A
Publication Date:
February 16, 2006
Filing Date:
July 29, 2005
Export Citation:
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Assignee:
IBM
International Classes:
H01L29/786; H01L21/336; H01L21/76; H01L21/762; H01L21/8238; H01L27/08; H01L27/092
Domestic Patent References:
JPH10189766A1998-07-21
JPH10242472A1998-09-11
JP2003338561A2003-11-28
JP2001274403A2001-10-05
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno