To improve the usage efficiency of an FPGA(Field Programmable Gate Array) where a resource for a logic circuit and the number of external terminals are limited.

When mapping a logic circuit 101 including a test circuit to an FPGA 107, first, the logic circuit 101 is divided into a logic circuit 103 for normal operation and a logic circuit 104 for testing by a circuit separation process 102. Then, the logic circuit 103 for normal operation is mapped to the FPGA 107 before the logic circuit 104 for testing by a mapping priority process 105. After that, the logic circuit 104 for testing is added according to a non-used logic block, a non-used wiring, and a non-used external terminal by the FPGA 107 using a test circuit adding process 106, thus eliminating the influence of the wiring for testing for the wiring of the logic circuit 103 for normal operation.