METHOD AND MATERIALS USEFUL FOR CHIP STACKING, CHIP AND WAFER BONDING

Title:

METHOD AND MATERIALS USEFUL FOR CHIP STACKING, CHIP AND WAFER BONDING

Document Type and Number:

Japanese Patent JP2009111356

Kind Code:

A

Abstract:

To provide materials, and methods that use such materials, that are useful for forming chip stack structure, chip and wafer bonding and wafer thinning.

The surface of a substrate 10 is coated by a photosensitive polymer, having a weight-average molecular weight of 10,000-50,000, after removing the volatiles, and a development pattern is obtained. In the development process, a part 20 where the polymer is not removed, and gap parts 30, 40 where the polyMer is removed are formed and bake curing is performed. A bonding pad 50 is exposed. Another structure, such as lamination, is formed using the coated substrate by cure process. The cure process continues bridge, for example, in the first cure step and completes bonding at higher temperature in a second cure step.

Inventors:

APANIUS CHRIS
SHICK ROBERT A
NG HENDRA
BELL ANDREW
WEI CHANG
NEAL PHILLIP S

Application Number:

JP2008241926A

Publication Date:

May 21, 2009

Filing Date:

September 22, 2008

Export Citation:

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Assignee:

PROMERUS LLC

International Classes:

H01L25/065; C08F32/00; H01L25/07; H01L25/18

Domestic Patent References:

JP2006022310A	2006-01-26
JP2005347442A	2005-12-15
JPH0435474A	1992-02-06
JP2009530864A	2009-08-27

Foreign References:

WO2006040986A1

2006-04-20

Attorney, Agent or Firm:

Sonoda Yoshitaka
Kobayashi Yoshinori

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