Title:
METHOD FOR OPERATING PROCESSOR OF TYPE INCLUDING BUS UNIT AND EXECUTION UNIT, CENTRAL PROCESSING UNIT, COMPUTER SYSTEM AND CLOCK CONTROLLER CIRCUIT
Document Type and Number:
Japanese Patent JP3454866
Kind Code:
B2
Abstract:
PURPOSE: To provide the clock controller circuit saving power of a high performance microprocessor.
CONSTITUTION: In this invention, when an execution unit 12 or an ALU cannot use data, two logic gates and one flip-flop are used to disable a clock signal to the execution unit 12 or the ALU. When a memory device, an I/O or an internal cache cannot provide data or an instruction to the execution unit 12, a sleep mode or a clock idle mode is provided to the execution unit 12. A clock controller circuit 26 gates the clock signal to a logical high level to disable the clock signal The clock controller circuit 26 stops the clock signal in response to a data use disable signal from a bus unit and a data request generating signal from the execution unit 12.
Inventors:
James Earl McDonald
Application Number:
JP15238693A
Publication Date:
October 06, 2003
Filing Date:
June 23, 1993
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
G06F1/04; G06F1/32; G06F9/38; (IPC1-7): G06F1/32; G06F1/04
Domestic Patent References:
| JP452915A | ||||
| JP3123919A | ||||
| JP62169219A | ||||
| JP466615U |
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)