Title:
METHOD OF OPTIMIZING MACRO TERMINAL ARRANGEMENT
Document Type and Number:
Japanese Patent JP2004086755
Kind Code:
A
Abstract:
To flexibly optimize the positions of terminals in the development of a macro by a bottom-up method without requiring any one-chip data.
The temporary macro size of the macro in an IC chip is determined (S1), the terminals of the macro are grouped for each connection (S3), arrangement information 11 in which an arrangement area is determined (S4) in a form surrounding the macro is prepared for each group, and based on the arrangement information 11, the optimum arrangement coordinates of the terminal positions of the macro are calculated under specified arrangement conditions. Thus, the terminals can be arranged optimally.
Inventors:
UMEDA MORIKATSU
Application Number:
JP2002249454A
Publication Date:
March 18, 2004
Filing Date:
August 28, 2002
Export Citation:
Assignee:
NEC MICROSYSTEMS LTD
International Classes:
G06F17/50; H01L21/82; (IPC1-7): G06F17/50; H01L21/82
Attorney, Agent or Firm:
Masahiko Desk
Yasuhisa Tanizawa
Kawai Nobuaki
Yasuhisa Tanizawa
Kawai Nobuaki
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