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Patent Searching and Data


Title:
METHOD FOR PROCESSING NEST STRUCTURE
Document Type and Number:
Japanese Patent JPS643736
Kind Code:
A
Abstract:

PURPOSE: To reduce the size of an internal information area and also to decrease the disk input/output frequency by excluding a table out of a nest and superscribing the table information on the called side when the table calling side has no process to be carried out next.

CONSTITUTION: A processor excludes the relevant table information out of a nest as long as no process to be carried out next exists in execution of the nest structure. Then the processor superscribes the next information into the area for the excluded table information. In other words, a table Z is called out and an output D is carried out based on the decision of conditions 5 and 6. Then the presence or absence is checked for the process to be carried out next. When said process is confirmed, an internal area is advanced. While the internal area kept under use is used as it is. In this case, the table Z has no process to be carried out next and therefore is excluded out of the nest. Thus a table X is used instead and an output B is carried out to complete the next processing. As a result, the table Z is superscribed at the part of a table Y in the internal area and the table area is reduced down to two faces. Then the input/output frequency of the table information is reduced down to four times as X→Y→Z→X. Thus the disk input/output frequency can be reduced.


Inventors:
ABE TETSUYA
ASANO TETSUYA
Application Number:
JP15888987A
Publication Date:
January 09, 1989
Filing Date:
June 26, 1987
Export Citation:
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Assignee:
MEIDENSHA ELECTRIC MFG CO LTD
International Classes:
G06F9/32; (IPC1-7): G06F9/32
Attorney, Agent or Firm:
Fujiya Shiga