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Title:
METHOD FOR PRODUCING TEST PATTERN, INFORMATION PROCESSOR, INTEGRATED CIRCUIT TESTING SYSTEM, PROGRAM AND RECORDING MEDIUM
Document Type and Number:
Japanese Patent JP2005156239
Kind Code:
A
Abstract:

To resolve the problem wherein large amount of time and labor are required, when producing a test pattern of a circuit part as object of mask option.

A method is for producing a test pattern used in the case of testing, with a specific test device, integrated circuits produced based on the mask pattern. The information processing device produces in advance, a net list set in non-wired state for a circuit inside, capable of changing wiring and objecting the mask option among the integrated circuits. To make the non-wired state location in the circuit inside in the net list into a wired state, logic synthesis is executed, based on the net list and the wiring information obtained from the mask option data including the wiring information in the circuit inside. A specific simulation is conducted to the net list after the logical synthesis. The test pattern is produced, based on the executed results of the simulation.


Inventors:
TSUCHIYA MASAHIRO
Application Number:
JP2003392402A
Publication Date:
June 16, 2005
Filing Date:
November 21, 2003
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
G01R31/28; G06F11/22; G01R31/3183; (IPC1-7): G01R31/3183; G01R31/28; G06F11/22
Attorney, Agent or Firm:
Isshiki International Patent Service Corporation