Title:
METHOD FOR REDUCING ABNORMAL NARROW-CHANNEL EFFECT IN P-TYPEMOSFET HAVING BURIED-CHANNEL BOUNDED BY TRENCH
Document Type and Number:
Japanese Patent JPH08241986
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a method for reducing anomalous sensitivity to a sidewise width in a buried channel p-type MOSFET. SOLUTION: After a deep phosphorous n-type channel is doped, a low- temperature annealing step is carried out using an inert gas. A boron buried channel is doped, and a gate oxidization step is carried out. Then a low temperature annealing step is selectively carried out between the boron-buried channel doping and the gate oxidization. A deep phosphorous n-type well is doped, and a boron-buried channel is doped. In an rapid thermal oxidization(RTO) step, gate oxidization is carried out. A gate oxidization step at 850 deg.C is selectively carried out just after the rapid thermal oxidization(RTO) step.
Inventors:
YOHAN ARUSUMAIAA
JIYATSUKU EE MANDERUMAN
JIYATSUKU EE MANDERUMAN
Application Number:
JP31799795A
Publication Date:
September 17, 1996
Filing Date:
December 06, 1995
Export Citation:
Assignee:
SIEMENS AG
IBM
IBM
International Classes:
H01L21/8234; H01L21/8242; H01L29/78; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Toshio Yano (2 outside)
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