PURPOSE: To reduce errors in reading bi-phase modulated signals, by selecting n-pieces of data which are simultaneously read out one bit by one bit from each memory in accordance with the most majority logic after successively writing bi-phase modulated signals which are discriminated as proper and supplied intermittently for n-times in the n-pieces of memories by a fixed word number.

CONSTITUTION: Bi-phase modulated signals (VPS data) shown by Fig. (a) arrive at an input terminal 1 and the first-half and second-half logical values of the each bit period of the data (a) are respectively stored in shift registers (SR) 2 and 3. The stores data are simultaneously supplied to an element checking circuit 6 one bit by one bit. When the logical values of the signals are different from each other, the circuit 6 judges that the signals are proper ones and successively writes the proper data only in one of memories 8∼10. The circuit 6 performs the above-mentioned operation whenever 15-word 120-bit VPS data arrive and, when the writing is completed, the stored data are simultaneously read out from the memories one bit by one bit and supplied to a majority logic circuit 11. The circuit 11 is supplied with the data shown by Figs. (b), (c), and (d) from the memories 8, 9, and 10 and outputs the data (h) having the largest logical value among the data (b), (c), and (d). The pulse (h) shows the same logical value as the input signal (a) has.