Title:
METHOD OF REDUCING VOIDS AND OTHER DEFECTS BY FILLING THROUGH-HOLE
Document Type and Number:
Japanese Patent JP2019214795
Kind Code:
A
Abstract:
To provide a method of improving through-hole filling of a substrate such as a printed circuit board.SOLUTION: The direct-current plating method suppresses the formation of voids, reduces dimples, and eliminates nodules. The method involves electroplating copper at a high current density, followed by a pause in electroplating and then turning on the current to electroplate at a lower current density to fill through-holes.SELECTED DRAWING: Figure 2
Inventors:
NAGARAJAN JAYARAJU
LEON BARSTAD
ZUHRA NIAZIMBETOVA
JOANNA DZIEWISZEK
LEON BARSTAD
ZUHRA NIAZIMBETOVA
JOANNA DZIEWISZEK
Application Number:
JP2019152769A
Publication Date:
December 19, 2019
Filing Date:
August 23, 2019
Export Citation:
Assignee:
ROHM & HAAS ELECT MAT
International Classes:
C25D5/18; C25D7/00; H05K3/40; H05K3/42
Attorney, Agent or Firm:
Patent Business Corporation Sender International Patent Office