Title:
METHOD FOR REDUCTION OF SPURIOUS SIGNAL GENERATED BY DIGITAL SIGNAL PROCESSOR
Document Type and Number:
Japanese Patent JPH0629842
Kind Code:
A
Abstract:
PURPOSE: To reduce spurious signals which are produced by changes of power consumption due to the cyclic operation of a processor. CONSTITUTION: A digital signal processor that depends on a command code to be executed carries out a circulatively repeated program routine BP which is initialized by an interrupt INT. A 1st mean power consumption Im is produced for an operation time, and the operating time, which is shorter than a time between two continuous interrupts, of the routine BP is produced by power consumption of the digital signal processor. The processor performs a waiting routine AWAIT that produces mean power consumption of the processor which corresponds to the consumption Im in the program routine period between continuous program routines BP.
Inventors:
HILPERT THOMAS DIPL-ING (DE)
MUELLER STEFAN DIPL-ING (DE)
BECHER JUERGEN (DE)
GEHRIG WILFRIED W (DE)
MUELLER STEFAN DIPL-ING (DE)
BECHER JUERGEN (DE)
GEHRIG WILFRIED W (DE)
Application Number:
JP9985793A
Publication Date:
February 04, 1994
Filing Date:
April 26, 1993
Export Citation:
Assignee:
ITT IND GMBH DEUTSCHE (DE)
International Classes:
G06F11/00; H03M1/08; G06J1/00; (IPC1-7): H03M1/08
Attorney, Agent or Firm:
Takehiko Suzue
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