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Title:
METHOD FOR SELF-TEST OF MEMORY
Document Type and Number:
Japanese Patent JP2002197893
Kind Code:
A
Abstract:

To realize reduction of chip area, shortening of a test time, and reduction of a cost by a method for an embeded self-test of a memory by which a defective bit can be detected, analyzed, and restored.

An incorporated self-test bit is enabled, an address and data are generated in a write period, data is written in an address position of a test memory as memory data, the memory data is read in a read period and compared with original data, when both accords in the compared result, end of a test of a test memory is decided, when a test memory is not ended, a process is returned to a write period, all test operation is stopped after end of the test memory, when it is not accordant, an error flag is set, while an error flag, address data, address end data, bit data are outputted, end of output of bit data is decided, when output of bit data is not ended, a process is returned to a process of discord, the error flag is set after finish of output of data, and a process is returned to a process of coincidence.


Inventors:
KAN HEN
Application Number:
JP2000389497A
Publication Date:
July 12, 2002
Filing Date:
December 21, 2000
Export Citation:
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Assignee:
KAN HEN
International Classes:
G01R31/3183; G06F11/22; G06F12/16; G11C29/00; G11C29/02; G11C29/12; G01R31/28; (IPC1-7): G11C29/00; G01R31/28; G01R31/3183; G06F11/22; G06F12/16
Attorney, Agent or Firm:
Masatake Shiga (7 outside)