Title:
METHOD AND STRUCTURE FOR SYNCHRONIZING SIGNAL
Document Type and Number:
Japanese Patent JP3945874
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To synchronize a serial data signal with a clock signal and to transmit serial data with a single channel at a high speed.
SOLUTION: Serial data is synchronized with a clock signal in a synchronizing circuit 10. Synchronization is accomplished by generating plural delayed things of the serial data signal by using delaying elements 21 to 27 which are serially connected. A delayed serial data signal is sampled by using a set of flip-flops 11 to 18. A sampled and delayed data signal which appears at an output of each flip-flop of a set of flip-flops 11 to 18 is used to decide which delayed data signal aligns the closest to a clock signal. An output of a multiplexer 40 is an alignment serial data signal. Further, a drift correcting circuit always monitors and corrects an alignment between the clock signal and the alignment serial data signal.
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Inventors:
David Kay Ford
Philip A. Jeffrey
Fax Sea Fam
Philip A. Jeffrey
Fax Sea Fam
Application Number:
JP27397397A
Publication Date:
July 18, 2007
Filing Date:
September 19, 1997
Export Citation:
Assignee:
Semiconductor Components Industries LLC
International Classes:
G06F13/42; H04L7/02; H04L7/027; H04L7/033; (IPC1-7): H04L7/027; G06F13/42
Domestic Patent References:
| JP4301941A | ||||
| JP3117129A | ||||
| JP55500724A | ||||
| JP4079632A | ||||
| JP60098716A | ||||
| JP64067029A | ||||
| JP61296815A | ||||
| JP61152127A |
Attorney, Agent or Firm:
Yoshiaki Ikeuchi