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Patent Searching and Data


Title:
METHOD AND SYSTEM FOR CALIBRATING LINEAR DELAY LINE
Document Type and Number:
Japanese Patent JPH03282272
Kind Code:
A
Abstract:

PURPOSE: To eliminate system error by providing means for regulating the variation rate of first ramp voltage connected with a first voltage generating means and a ramp count means.

CONSTITUTION: Sequential repetitive calculation is performed over several calibration cycles until a correction coefficient (dk) in an up/down counter 138 goes zero. Consequently, system calibration is ensured. The calibration circuit adds less than 200 gates to the circuit shown on the drawing and generates current correction coefficients in leading mode. The calibration is independent from the signal propagation lag (Tα1, Tα2), the charging/discharging characteristics (Tw1, Tw2) and the nonlinearity of a ramp generator. Nonlinearity at the linear part of ramp has effect not on the calibration of range but only on the linearity of timing resolution. Consequently, system error is eliminated.


Inventors:
FUANNWAA ANSONII RUU
Application Number:
JP25401090A
Publication Date:
December 12, 1991
Filing Date:
September 21, 1990
Export Citation:
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Assignee:
SHIYURANBAAGAA TEKUNOROJIIZU I
International Classes:
G01R31/28; G01R31/319; G01R35/00; H03H11/26; (IPC1-7): G01R31/28; H03H11/26
Attorney, Agent or Firm:
Kazuo Kobashi (1 person outside)