Title:
METHOD AND SYSTEM FOR CONTROLLING PROCESS OF SEMICONDUCTOR SILICON SINGLE-CRYSTAL WAFER
Document Type and Number:
Japanese Patent JP3419241
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To eliminate the delay of delivery and a blank between wafer processes and to make constant a machining treatment speed by providing a stocker for storing a wafer temporarily and performing the lot control of wafer units.
SOLUTION: When a cassette stocker is stored, a wafer after being subjected to an orientation measurement and a primary chamfering at a sub process travels through a process consisting of a lap, a secondary chamfering, an etching, a mirror-surface chamfering, a mirror surface polishing, a primary washing, and a quality inspection in lot units in an entire process, is subjected to machining treatment in the minimum unit lots in each unit process, and is stored in a clean stocker. In this case, conformance/non-conformance are judged by examining the quality inspection result based on a product standard, and non-conforming articles are returned to a mirror- surface polishing process in the minimum unit lots and are machined again. Conforming articles are reorganized in the minimum unit lots at a sub process and are delivered to a customer through the processes of a final washing, a packaging, and a shipment, thus eliminating the problems of the delay of delivery and a blank between wafer processes and improving productivity.
Inventors:
Kohei Toyama
Application Number:
JP8332397A
Publication Date:
June 23, 2003
Filing Date:
March 17, 1997
Export Citation:
Assignee:
Shin-Etsu Semiconductor Co., Ltd.
International Classes:
H01L21/304; H01L21/00; H01L21/02; (IPC1-7): H01L21/02
Domestic Patent References:
| JP5121521A | ||||
| JP6166600A | ||||
| JP969557A | ||||
| JP8181093A |
Attorney, Agent or Firm:
Mikio Yoshimiya
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